1. Field of the Invention
The present invention relates to a word line voltage supply circuit for supplying a predetermined driving voltage to word lines of, for example, an asynchronous static random access memory (SRAM).
2. Description of the Related Art
In recent years, along with the reduction of power supply voltages, asynchronous SRAMs have been developed for improving the stability of operations by using booster circuit technology. In a memory cell of an SRAM, the holding characteristic of storage data tends to become unstable when operating at a low power supply voltage. To avoid this, measures such as using a booster circuit to generate a voltage higher than the power supply voltage and supply it to selected word lines are generally devised.
FIG. 12 is a circuit diagram of an example of the configuration of an SRAM memory cell. Note that, here, a memory cell of a high resistance load type SRAM is shown as an example.
As illustrated, the memory cell MC of a high resistance load type SRAM is constituted by n-channel MOS transistors (hereinafter simply referred to as nMOS transistors) TR1, TR2, TR3, and TR4 and resistors R1 and R2. The resistors R1 and R2 are high value resistors formed by, for example, polycrystalline silicon and constitute load elements of the transistors TR1 and TR2, respectively. In the memory cell MC, nodes N1 and N2 constitute storage nodes. The storage nodes N1 and N2 are connected to a bit line BL and a bit line/BL (hereinafter referred to as bit sub line/BL) through the transistors TR3 and TR4. The transistors TR3 and TR4 are connected to the word line WL at their gates and are controlled in on/off states according to the voltage supplied to the word line WL. Note that the transistors TR3 and TR4 are also called access transistors. The storage nodes N1 and N2 are set at levels according to the write data due to a write operation.
For example, the bit line BL is set at a high level, for example, the level of a power supply voltage Vcc while the bit sub line/BL is set at a low level, for example, the level of the ground GND, according to the write data. After the levels of the bit line and the bit sub line become finally determined, since the word line WL is set at a high level by a decoder, the access transistors TR3 and TR4 are held in the on state. Therefore, the levels of the bit line BL and the bit sub line/BL are output to the storage nodes N1 and N2. In the situation mentioned above, the storage node N1 is set at the high level while the storage node N2 is set at the low level, respectively. When the levels of the storage nodes N1 and N2 are finally determined, the word line WL is switched to the low level and the transistors TR3 and TR4 are held at the off states. The levels of the storage nodes N1 and N2 are held by the memory cell MC.
Here, by defining the state of the storage node N1 being the high level and the storage node N2 being the low level as the data "1" while defining the state of the storage node N1 being the low level and the storage node N2 being the high level as the data "0", 1 bit of information can be stored by the memory cell MC. Furthermore, since the levels of the storage nodes are held, information in accordance with the levels of the storage nodes is stored by the memory cell MC until the next rewrite operation.
In the memory cell MC of the SRAM mentioned above, there is a disadvantage that along with the reduction in the power supply voltage, the data write operation becomes uncertain or the data holding characteristic becomes unstable.
Due to the reduction of the power supply voltage, the level of the voltage of the signal supplied to the selected word line becomes lower during a write operation. Along with this, the voltage of the signal input to the storage nodes of the memory cell becomes lower. For example, in a write operation, when the bit line BL is held at the level of the power supply voltage Vcc according to the write data and a write pulse having the level of the power supply voltage is input to the selected word line, the storage node N1 is supplied with a voltage of a level of (Vcc-Vth). Here, Vth is a threshold voltage of the transistor TR3 including the substrate bias effect. Along with the reduction of the power supply voltage Vcc, the voltage loss due to the threshold voltage Vth of the access transistors TR3, TR4 becomes relatively larger. Therefore, when the power supply voltage Vcc becomes lower, the level of the voltage set in the storage node N1 also becomes lower, and the data holding characteristic of the memory cell becomes unstable.
Further, in a read operation, since a large operating voltage cannot be taken out from the bit line BL or the bit sub line/BL, the operating stability of the sense amplifier or other amplification circuit connected to the bit line BL and the bit sub line /BL deteriorates, erroneous operations readily occur, and there is a possibility of error occurring in the read data.